<br>Chapter 1 Introduction to Interconnection Networks <br>1.1 Three Questions About Interconnection Networks <br>1.2 Uses of Interconnection Networks <br>1.3 Network Basics <br>1.4 History <br>1.5 Organization of this Book <br><br>Chapter 2 A Simple Interconnection Network <br>2.1 Network Specifications and Constraints <br>2.2 Topology <br>2.3 Routing <br>2.4 Flow Control <br>2.5 Router Design <br>2.6 Performance Analysis <br>2.7 Exercises <br><br>Chapter 3 Topology Basics <br>3.1 Nomenclature <br>3.2 Traffic Patterns <br>3.3 Performance <br>3.4 Packaging Cost <br>3.5 Case Study: The SGI Origin 2000 <br>3.6 Bibliographic Notes <br>3.7 Exercises <br><br>Chapter 4 Butterfly Networks <br>4.1 The Structure of Butterfly Networks <br>4.2 Isomorphic Butterflies <br>4.3 Performance and Packaging Cost <br>4.4 Path Diversity and Extra Stages <br>4.5 Case Study: The BBN Butterfly <br>4.6 Bibliographic Notes <br>4.7 Exercises <br><br>Chapter 5 Torus Networks <br>5.1 The Structure of Torus Networks <br>5.2 Performance <br>5.3 Building Mesh and Torus Networks <br>5.4 Express Cubes <br>5.5 Case Study: The MIT J-Machine <br>5.6 Bibliographic Notes <br>5.7 Exercises <br>Chapter 6 Non-Blocking Networks <br>6.1 Non-Blocking vs. Non-Interfering Networks <br>6.2 Crossbar Networks <br>6.3 Clos Networks <br>6.4 Benes Networks <br>6.5 Sorting Networks <br>6.6 Case Study: The Velio VC2002 (Zeus) Grooming Switch <br>6.7 Bibliographic Notes <br>6.8 Exercises <br><br>Chapter 7 Slicing and Dicing <br>7.1 Concentrators and Distributors <br>7.2 Slicing and Dicing <br>7.3 Slicing Multistage Networks <br>7.4 Case Study: Bit Slicing in the Tiny Tera <br>7.5 Bibliographic Notes <br>7.6 Exercises <br><br>Chapter 8 Routing Basics <br>8.1 A Routing Example <br>8.2 Taxonomy of Routing Algorithms <br>8.3 The Routing Relation <br>8.4 Deterministic Routing <br>8.5 Case Study: Dimension-Order Routing in the Cray T3D <br>8.6 Bibliographic Notes <br>8.7 Exercises <br><br>Chapter 9 Oblivious Routing <br>9.1 Valiant's Randomized Routing Algorithm <br>9.2 Minimal Oblivious Routing <br>9.3 Load-Balanced Oblivious Routing <br>9.4 Analysis of Oblivious Routing <br>9.5 Case Study: Oblivious Routing in the<br>Avici Terabit Switch Router(TSR) <br>9.6 Bibliographic Notes <br>9.7 Exercises <br><br>Chapter 10 Adaptive Routing <br>10.1 Adaptive Routing Basics <br>10.2 Minimal Adaptive Routing <br>10.3 Fully Adaptive Routing <br>10.4 Load-Balanced Adaptive Routing <br>10.5 Search-Based Routing <br>10.6 Case Study: Adaptive Routing in the<br>Thinking Machines CM-5 <br>10.7 Bibliographic Notes <br>10.8 Exercises <br><br>Chapter 11 Routing Mechanics <br>11.1 Table-Based Routing <br>11.2 Algorithmic Routing <br>11.3 Case Study: Oblivious Source Routing in the<br>IBM Vulcan Network <br>11.4 Bibliographic Notes <br>11.5 Exercises <br><br>Chapter 12 Flow Control Basics <br>12.1 Resources and Allocation Units <br>12.2 Bufferless Flow Control <br>12.3 Circuit Switching <br>12.4 Bibliographic Notes <br>12.5 Exercises <br><br>Chapter 13 Buffered Flow Control <br>13.1 Packet-Buffer Flow Control <br>13.2 Flit-Buffer Flow Control <br>13.3 Buffer Management and Backpressure <br>13.4 Flit-Reservation Flow Control <br>13.5 Bibliographic Notes <br>13.6 Exercises <br><br>Chapter 14 Deadlock and Livelock <br>14.1 Deadlock <br>14.2 Deadlock Avoidance <br>14.3 Adaptive Routing <br>14.4 Deadlock Recovery <br>14.5 Livelock <br>14.6 Case Study: Deadlock Avoidance in the Cray T3E <br>14.7 Bibliographic Notes <br>14.8 Exercises <br><br>Chapter 15 Quality of Service <br>15.1 Service Classes and Service Contracts <br>15.2 Burstiness and Network Delays <br>15.3 Implementation of Guaranteed Services <br>15.4 Implementation of Best-Effort Services <br>15.5 Separation of Resources <br>15.6 Case Study: ATM Service Classes <br>15.7 Case Study: Virtual Networks in the Avici TSR <br>15.8 Bibliographic Notes <br>15.9 Exercises <br><br>Chapter 16 Router Architecture <br>16.1 Basic Router Architecture <br>16.2 Stalls <br>16.3 Closing the Loop with Credits <br>16.4 Reallocating a Channel <br>16.5 Speculation and Lookahead <br>16.6 Flit and Credit Encoding <br>16.7 Case Study: The Alpha 21364 Router <br>16.8 Bibliographic Notes <br>16.9 Exercises <br><br>Chapter 17 Router Datapath Components <br>17.1 Input Buffer Organization <br>17.2 Switches <br>17.3 Output Organization <br>17.4 Case Study: The Datapath of the IBM Colony<br>Router <br>17.5 Bibliographic Notes <br>17.6 Exercises <br><br>Chapter 18 Arbitration <br>18.1 Arbitration Timing <br>18.2 Fairness <br>18.3 Fixed Priority Arbiter <br>18.4 Variable Priority Iterative Arbiters <br>18.5 Matrix Arbiter <br>18.6 Queuing Arbiter <br>18.7 Exercises <br><br>Chapter 19 Allocation <br>19.1 Representations<br>19.2 Exact Algorithms<br>19.3 Separable Allocators <br>19.4 Wavefront Allocator <br>19.5 Incremental vs. Batch Allocation <br>19.6 Multistage Allocation <br>19.7 Performance of Allocators <br>19.8 Case Study: The Tiny Tera Allocator <br>19.9 Bibliographic Notes <br>19.10 Exercises<br><br>Chapter 20 Network Interfaces <br>20.1 Processor-Network Interface <br>20.2 Shared-Memory Interface <br>20.3 Line-Fabric Interface <br>20.4 Case Study: The MIT M-Machine Network Interface <br>20.5 Bibliographic Notes <br>20.6 Exercises <br><br>Chapter 21 Error Control 411<br>21.1 Know Thy Enemy: Failure Modes and Fault Models <br>21.2 The Error Control Process: Detection, Containment,<br>and Recovery <br>21.3 Link Level Error Control <br>21.4 Router Error Control <br>21.5 Network-Level Error Control <br>21.6 End-to-end Error Control <br>21.7 Bibliographic Notes <br>21.8 Exercises <br><br>Chapter 22 Buses <br>22.1 Bus Basics <br>22.2 Bus Arbitration <br>22.3 High Performance Bus Protocol <br>22.4 From Buses to Networks <br>22.5 Case Study: The PCI Bus <br>22.6 Bibliographic Notes <br>22.7 Exercises <br><br>Chapter 23 Performance Analysis <br>23.1 Measures of Interconnection Network Performance <br>23.2 Analysis <br>23.3 Validation<br>23.4 Case Study: Efficiency and Loss in the<br>BBN Monarch Network <br>23.5 Bibliographic Notes <br>23.6 Exercises <br><br>Chapter 24 Simulation <br>24.1 Levels of Detail <br>24.2 Network Workloads <br>24.3 Simulation Measurements <br>24.4 Simulator Design <br>24.5 Bibliographic Notes <br>24.6 Exercises <br><br>Chapter 25 Simulation Examples 495<br>25.1 Routing<br>25.2 Flow Control Performance <br>25.3 Fault Tolerance <br><br>Appendix A Nomenclature <br>Appendix B Glossary <br>Appendix C Network Simulator